With shrinking geometries of IC devices to quarter micron and below, shallow trench insulation (STI) technique is widely used to isolate IC elements on the wafer substrate level. Conventional STI fabrication methods comprises forming a pad oxide on the surface of a silicon substrate, forming a nitride polish stop layer, forming STI trenches by anisotropic etching of the nitride polish stop layer and a certain depth of the wafer substrate, typically to a depth of 3000 Å. Thermal oxide liner is then formed in the trench, and optionally a thin nitride liner, and is then filled with silicon oxide insulating material. STI chemical mechanical polishing (CMP) is then implemented and the nitride layer (defining the active regions) and pad oxide removed. A sacrificial thermal oxide layer typically 150 Å to 250 Å thick is grown followed by various masking, ion implantation and cleaning steps. The cleaning steps of isotropic nature cause oxide loss at top corners of the STI leading to divot formation. The divot severity increases with each clean step and longer cleaning time. The enhanced field oxide etch rate due to ion implantation doping further exacerbates the problem.
The divots are detrimental, particularly at low voltage region with the most severe recess, where circuitries and elements such as memory array, capacitors and etc. will typically be formed. Divots negatively influence among others junction leakage, junction breakdown and threshold voltage.
STI field step height difference between different regions and to substrate poses great challenge to patterning of gate poly features. Minimum photo resist thickness is desired to achieve better focus margin, and is typically limited by the minimum thickness required to mask the gate poly etch by reactive ion etch (RIE). Photo resist thickness has to be increase to cater for the step height difference at the expense of focus margin. Another key challenge due to the step height difference is the resulting gate poly width after gate poly etch (not described). It is not uncommon to observe gate poly width increase of 5 nm or more when the gate poly line traverses from substrate region to STI field region. This potentially causes subsequent inter-level dielectric (ILD) gap fill issue and electrical characteristic mismatch to design characteristic.
According to US 2005/196928 A1 a STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer, e.g. having a thickness less than 400 Å. The very thin nitride polish stop layer is retained in place during subsequent masking, implanting and cleaning steps to form dopant regions, and is removed prior to gate oxide and gate electrode formation. In particular the method of fabricating a semiconductor device comprises: forming a nitride polish stop layer, at a thickness no greater than 400 Å, over a semiconductor substrate; forming an opening in the nitride polish stop layer and a trench in the substrate; filling the trench with insulating material forming an overburden on the nitride polish stop layer; and polishing to form an upper planar surface stopping of the nitride polish stop layer, thereby forming a shallow trench isolation region. The nitride polish stop layer is formed at a thickness of 50 Å to 150 Å.
A drawback of the above method is that a sufficiently thick buffer layer is required to compensate subsequent oxide loss during conventional dual or triple gate oxidation process, gate poly sidewall formation and silicidation. This is particularly critical for LV regions where typically low voltage transistors are defined. Higher ion implant energies will be needed leading the higher implanted ion spread in the substrate. Also, removing the nitride stop and pad oxide layer relieve stress from the substrate.
Furthermore, a sacrificial oxide is grown as implant buffer by conventional method. The exposed STI field oxide is subjected to many masking, ion implantation, wet cleaning and gate oxidation HF cleans leading to divots formation and field step height imbalance at different regions.
The sacrificial oxide is removed prior to gate oxidation by wet clean. A sacrificial oxide of 200 Å thick typically leads to about 300 Å field oxide loss. High voltage (HV) thermal gate oxide (GOX) is first grown, and then removed from the low voltage (LV) and the intermediate voltage (MV) region by selective wet clean by masking. A typical 70 Å gate oxide leads to about 130 Å field oxide loss. MV thermal GOX is then grown, and then removed from the LV region by selective wet clean. A typical 65 Å MV GOX leads to about 110 Å field oxide loss. The LV thermal GOX is now grown and gate poly deposited. The LV region has now a potential divot recess of more than 540 Å and a field step height difference of 240 Å or more relative to the HV region. The HV region has a potential field step height difference of 540 Å or more relative to the substrate level.
According to US 2008/124872 A1 a method for forming TGO structures (triple gate oxide) includes providing a substrate containing regions of first, second and third kinds in which devices with respective first, second and third gate oxide layers of different thicknesses are to be formed. The second gate oxide layer is formed over the substrate and then removed from regions of the first kind where the first gate oxide layer is subsequently grown. A first conductive layer is deposited over the substrate. The first conductive layer and second gate oxide layer are subsequently removed from regions of the third kind. The third gate oxide layer followed by deposition of a second conductive layer is formed over the substrate and then removed except from over regions of the third kind. In particular the method of forming triple gate oxide (TGO) structures comprises: Providing a substrate comprising regions of a first kind, regions of a second kind, regions of a third kind, internal isolation regions which separate devices within each region and bounding isolation regions which separate devices of different regions; forming a second gate oxide layer said regions of the first, second and the third kind; removing said second gate oxide layer from said regions of the first kind; forming a first gate oxide layer over said regions of the first kind; forming a first conductive layer over said regions of the first, second and the third kind; removing said first conductive layer and said second gate oxide from said regions of the third kind; forming a third gate oxide layer; forming a second conductive layer over said regions of the first kind, said regions of the second kind and said regions of the third kind; removing said second conductive layer and said third gate oxide layer from said regions of the first kind and said regions of the second kind; forming a third conductive layer over said regions of the first kind, said regions of the second kind and said regions of the third kind; completing fabrication of devices in said regions of the first kind, said regions of the second kind and said regions of the third kind according to standard manufacturing procedures wherein the first, second and third gate oxide layers have different thickness, the first gate oxide layer being the thickest and the third gate oxide layer being the thinnest.
Therefore, a need exists for a fabrication method to minimize STI divots formation, STI field step height difference between different regions, and STI field step height difference to substrate.